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Figure 1 Three interlock structure (TILL) reinforcement latches
Fig. 2 Comparison of single particle inversion reinforcement efficiency of TILL and other structures
Recently, Yang Haigang, a researcher at the Institute of Electronics of the Chinese Academy of Sciences, led the team of programmable chips and systems to make a breakthrough in the field of deep sub-micron integrated circuit single particle flip-over reinforcement design technology. Researchers have proposed a novel three-interlock (TILL) structure latch that has been tested and shown to be more resistant than single-particle and synthetic “delay-area†latches for traditional dual interlock (DICE) structures that have been in use for more than 20 years. - The "soft error rate" performance indicator is increased by one order of magnitude.
Based on the results, the team's Ph.D. student Li Tianwen and the advisor Yang Haigang and three other R&D personnel published the paper A CMOS in IEEE Transactions on Nuclear Science (Vol.61, No.6, December 2014). Triple Inter-Locked Latch for SEU Insensitivity Design.
When the chip is used in a space environment, various cosmic rays and particles may hit and pass through the circuit, and ionization occurs on the track to generate an electron-hole pair. Absorption of these electron-hole pairs by the nodes of the circuit causes data errors in the sequential circuit and the memory circuit, resulting in malfunction or failure of the electronic system. This effect is called single event upset (SEU). As the integrated circuit manufacturing process node continues to decrease, the circuit is more susceptible to spatial radiation. The latch is a key timing unit in the large-scale integrated circuit, especially sensitive to the spatial single-particle effect. It is very important to improve its resistance to single-event inversion to the radiation resistance of the whole circuit.
The radiation-resistance reinforcement method can be divided into two types: special process and circuit design reinforcement. The process reinforcement uses a special chip production process line to reduce the collection of electron-hole pairs by the device. However, the production process of special process lines is more complex and often lags behind commercial processes, reducing chip integration. Therefore, the circuit design to achieve resistance to radiation has been rapidly developed.
Currently used latch design reinforcement methods include three-mode redundancy, Soft Error Masking (SEM), Schmitt Trigger (ST), and Dual Inter-locked Cell (DICE) technology. . The three-mode redundancy technique eliminates a single flipping error by most decision mechanisms, but it does not increase the flipping threshold of the basic cell, increases the area and power consumption, and reduces the speed, thereby limiting its application in large scale integrated circuits. . The SEM and ST structures are improved on the basis of common latches, increasing the node capacitance and feedback path delay, although the ability of the circuit node to resist flipping is improved, but the circuit performance is reduced. In the DICE structure, when two nodes are flipped at the same time, a functional error still occurs.
Li Tianwen, Ph.D. student under the guidance of the instructor Yang Haigang, through long-term in-depth research, continuous design optimization experiments, developed a novel Triple Inter-Locked Latch (TILL), as shown in Figure 1. This structure circuit compares single-particle flip-flop immunity occurring at multiple nodes with the performance of other conventional single-particle flip-flop reinforcement latches. The speed of the three-interlocked structure is increased by 24%, and the power delay product is smaller by 22%. Increase 17%. Comparative analysis shows that the three-interlocked structure has the highest reinforcement efficiency, as shown in Figure 2.
The test chip is designed using advanced standard CMOS technology. The single-particle turn-over threshold of the three-interlock reinforcement structure is greater than 42MeV-cm2/mg, and its flip section is at least one order of magnitude lower than the conventional reinforcement structure.
At present, the research results have been applied in the latest chip products of the research lab to further improve the space application reliability and anti-irradiation capability of the domestic “Huixin†series chips.
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UNS
WNR
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31
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1.4562
59
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2.4605
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2.4630
263
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2.4816
625
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2.4856
690
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825
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2.4858
718
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800
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1.4876
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